How to break the memory supercycle? Or is it even possible?

A few days ago, SK Group Chairman said that customers are asking for 4x-5x more supply, but wafer supply will only double by 2x by 2030.

So, I got quite curious about this, and I want to know if it really checks out or not. This is for fun, but I will try to keep the math and assumptions as realistic as possible (bears will still hate it, but it is what it is) and create a model from the ground up.

First, we will talk about current supply and how it's expected to grow (and could grow) over the next 4 years.

By the end of 2026, the Big 4 will have around 2M WPM of DRAM capacity. I expect this to grow to 4.8M WPM by 2030, comprising mainly of 1a/1b/1c/1d. 0a will likely hit the market in late 2030 or 2031.

Samsung

Samsung will end 2026 with around 720k WPM of DRAM capacity.

Samsung will add around 70k WPM (150k WPM total capacity) at P4 by 2027. P5 and P6/ P5 Fab 2 are mega fabs with 300k WPM nameplate capacity supporting both DRAM and NAND. Samsung will probably have a 2:1 DRAM/HBM: NAND ratio at 200k WPM for DRAM and 100k WPM for NAND. P5 will be fully ramped by 2028 or early 2029. P6/P5 Fab 2 will ramp completely by 2029 or early 2030. Samsung's Yongin Fab 1 will have around 150-200k WPM of DRAM capacity by 2030. I expect Samsung and the Korean government to accelerate the development of the Southwest/Gwangju Fab 1 Phase 1 and have at least 60k WPM capacity by 2030. I expect Samsung to add around 680K-730K WPM of DRAM capacity from 2027-2030, bringing its total DRAM capacity to 1.40M-1.45M WPM.

SK Hynix

SK Hynix will end 2026 with around 590k WPM of DRAM capacity.

SK Hynix will add around 50k WPM (total 90k) at M15X. Their Yongin Y1 mega Fab will have 6 cleanrooms supporting 60k WPM DRAM capacity each. I expect them to hasten the development of the Yongin Y2 mega fab and at least have 2 cleanrooms ready by 2030 (60k WPM capacity each). I also expect SK Hynix & the Korean government to accelerate Southwest/Gwangju Fab 1 Phase 1 and have at least 60k WPM capacity by 2030. I expect SK Hynix to add around 590k WPM by 2030 and basically double total capacity to 1.18M WPM.

Micron

Micron will end 2026 with around 375k WPM of DRAM capacity.

Micron will ramp the Hiroshima Fab to 150k WPM and the Manassas (legacy D1a) to 30k WPM. Micron's Idaho Fab 1 will have around 80k WPM DRAM capacity, and Idaho Fab 2 will also have around 80k WPM DRAM capacity. The PSMC Tongluo Fab 1 will add around 45k WPM, and Fab 2 will add another 40k-45k WPM. I expect them to hasten the development of the New York Mega Fab and have at least 2 cleanrooms ready by 2030, each contributing 50k WPM. Micron will add around 400k-405k WPM capacity by 2030 and have around 775k-780k WPM of total DRAM capacity.

CXMT & China

CXMT will end 2026 with around 350k WPM of DRAM capacity.

China is a lot harder to model and has the potential to add the most capacity, primarily because cleanroom construction time is around 12 months compared to 21-24 months in the Rest of the World. Capital isn't an issue for CXMT and YMTC. Since the ROI of a memory fab is so high now, financing it is extremely easy, with banks and various state funds joining in. Things also get more complicated as the Chinese government is forcing CXMT to transfer its DRAM technology to JHICC, Swaysure, and YTMC's subsidiary XMC to alleviate the shortage. Swaysure has just completed the buildout of its 140k WPM in Shenzhen, and JHICC's Jinjiang Fab has enough cleanroom space for 120k WPM. Although only Phase 1 (60k WPM) will be completed by the end of 2026, with equipment moved in. YMTC will have around 50k WPM of DRAM capacity at Wuhan Fab 3. Frankly, the biggest constraint for China is the availability of litho tools when it comes to scaling capacity. If the MATCH Act passes and DUV sales are banned, then it will derail CXMT's & China's memory expansion plans. But SMEE DUVi was shipped to CXMT & SMIC last year, and beta testing is nearly over, with mass production beginning from late 2026 or early 2027. Yuliangsheng/SiCarrier's DUVi is expected to enter mass production in 2028. I don't expect lithography to be a limiter when it comes to logic (5nm/7nm+) and memory (D1a/D1b/D1z) after 2028, but the MATCH Act can certainly derail near-term plans. Citrini Research published a great report on Chinese memory a few days ago( Citrini.com). Check it out.

Keeping the above in mind, my China model will have a large range. At a minimum, CXMT is expected to expand to Hefei Fab 3 (100k WPM) and maybe even develop a Fab 4 (100k WPM). Shanghai Fab is expected to expand from 50k to 400k by 2030 (rumors of 600k WPM are floating around). Beijing Fab is expected to expand to 200k WPM (rumors of 400k WPM are floating around). 600k WPM at Shanghai and 400k WPM at Beijing will largely depend on Chinese compute demand and CXMT's HBM maturity. CXMT is developing a new R&D line, which will free up about 50k WPM of aggregate capacity at Hefei Fab 1 and Fab 2. CXMT can potentially add 600k-1.1M WPM of DRAM capacity and have a total capacity of around 950k-1.45M WPM. Although the majority of this capacity will be at D1a, D1b, and maybe around 100k-150k WPM of D1c capacity with the help of 3D DRAM. YMTC has plans till Fab 8, and they are quickly bringing more cleanrooms online (refer to the Citrini.com article for more info). I expect them to build another 50k WPM DRAM facility, but determining the upside potential is extremely difficult. YMTC's DRAM capacity will likely reach 200k WPM. Swaysure and JHICC have Huawei backing and are directly supplying DRAM to Huawei. Huawei has huge incentives to invest. At a minimum, they will have 260k WPM of DRAM capacity by 2030. Upside is hard to determine, as SiCarrier/Yuliangsheng is an integrated WFE manufacturer as well, so they are less sensitive to WFE scarcity.

Demand

Adding up all the capacity, we get to around 4.8M WPM (base case) of DRAM capacity. It could go as high as 5.68M if China is completely unconstrained and CXMT's HBM roadmap is executed well. Elon's Terafab, Samsung's & SK Hynix's US investments are not included. I personally believe that their US investments will be focused on HBM packaging rather than memory fabs in exchange for no tariffs on semiconductors for Korea. HBM wafers will flow in from Korea, get stacked at their packaging facility in the US, and be sent to TSMC's Arizona facility.

Now comes the fun part. Accelerator sales are expected to hit 30M units by 2030. I expect 15M accelerators to have an average of 1TB of HBM4e and another 15M accelerators to have an average of 1.5TB of HBM5. Total demand will be 15EB of HBM4e and 22.5EB of HBM5. Agentic CPUs (Head node + standalone) are expected to reach a 1:1 CPU: GPU ratio and have around 2.5 TB of DDR6 memory per CPU. This will be around 75EB of demand. General cloud/IaaS CPU sales will also grow to 25M per year (up from 20M in 2026). They will have an average of 1 TB of DDR6 memory and constitute about 25EB in demand. Consumer DRAM demand is around 17-18 EB in 2026. I expect it to grow to 20EB by 2030 (although this level of growth means AI PCs/smarthphones have failed to take off, they will have to fight for supply from AI data centers. I don't think they will win). So we have an aggregate demand of 157.5 EB (75EB + 25EB + 22.5EB + 15EB + 20EB) by 2030.

As you can see, I haven't modeled any DRAM demand for physical AI (humanoids & autonomous cars), so even if my DC & AI demand estimates are too high (they are not), it will be balanced out by physical AI demand. ASML's 2030 DRAM demand forecast is around 130EB (26% CAGR bit growth). Supply was around 37EB in 2025 and is expected to grow to 44EB in 2026.

Supply Assumptions

First, we will talk about node density. D1a = 0.32 Gb/mm2, D1b = 0.43 Gb/mm2, D1c = 0.56 Gb/mm2, D1d = 0.7 Gb/mm2. I don't expect any meaningful 0a volume till 2030, so we will exclude it. Out of our 4.8M WPM case, I expect 2.5M WPM to be dedicated to D1c to support HBM4e/5 (2.5M WPM from the Big 3), 600K WPM to be dedicated to D1d, 870k dedicated to D1a (260k WPM from Swaysure/JHICC, 30k Micron, 400k from CXMT, 180k SK Hynix Wuxi), 700k WPM dedicated to D1b (400k from CXMT & 200k from YMTC, 100k WPM from Samsung) and CXMT may have around 150k WPM of D1c capacity through 3D DRAM.

You may know that HBM dies are about 35%-45% larger than equal-capacity DDR5 dies, as TSVs and ultra-wide I/Os consume more silicon area. Fewer dies fit per wafer, and TSV processing and stacking heavily reduce the net yield. Combining this, around 2.7x more effective DRAM wafer capacity is needed to deliver the same number of good memory bits for HBM3E. This multiplier grows to 4x for HBM4E and even more for HBM5 as the interface width doubles from 2048 to 4096. But for simplicity's sake, we will consider only a 4x multiplier.

Micron

At 95% D1c yield, we need around 31.91M wafer starts per year or 2.66M WPM D1c capacity to produce around 37.5 EB of HBM4E & HBM5. I expect the Big 3 to allocate around 2.5M WPM capacity, and Samsung could convert its 100k WPM of D1b capacity to D1c.

At 85% D1d yield and 600k WPM capacity, 3.15 EB/month or 37.85 EB/year can be produced. At 70% D1b yield and 600k WPM capacity (CXMT + YMTC), 1.596 EB/month or 19.14 EB/year can be produced. At 95% D1b yield and 100k WPM capacity, 0.36 EB/month or 4.3 EB/year can be produced. At 80% D1a yield and 660k WPM (400k CXMT and 120k WPM JHICC, 140k WPM), 1.493 EB/month or 17.91 EB/year of DRAM can be produced. At 95% yield and 210k WPM (180k WPM Hynix Wuxi and 30k WPM Micron Manassas), 0.564 EB/month or 6.77 EB/year of DRAM can be produced. At 60% D1c yield and 150k WPM capacity (CXMT 3D DRAM), 0.445 EB/month or 5.34 EB/year of DRAM can be produced. Adding all of it up, we get around 91.31 EB/year of general DRAM supply compared to 120EB/year of DRAM demand.

There is a possibility (at least rumors) that China can expand faster with CXMT expanding Shanghai Fab to 600k WPM, Beijing Fab to 400k WPM, and building Hefei Fab 4. YMTC adds 50k WPM DRAM capacity at Fab 7 and Fab 8 each. JHICC will implement its Fab 2 plans (120K WPM), and Swaysure will build another 140k WPM fab. This will add another 860k WPM of incremental D1b capacity, and at 70% yield, this will be around 27.54 EB/year of DRAM capacity. This will cause the DRAM market to go from a 28.69 EB deficit to a deficit of 1.19 EB. But you may have observed that I haven't really talked about Chinese HBM demand (the expansion of CXMT Shanghai and Beijing fab and YMTC/XMC capacity is heavily dependent on that). I expect China to have at least 7EB-10EB/year of HBM demand, and this incremental 860k WPM can supply around 7 EB/year of demand.

Implications

As you can probably tell, this is extremely bullish for WFE demand and the biggest constraint for bringing around 2.8M-3.66M WPM of incremental DRAM supply. Secondly, China will also enter the Western server DRAM supply chain as the vast majority of the Big 3's wafer capacity (70%) will go towards serving HBM demand unless they expand faster. (I have already incorporated accelerated expansion for the Big 3)

DRAM Market Size in 2030

I expect a 25% deficit for the general DRAM market. 91EB/year of supply versus 120EB/yr of demand. DRAM ASP will remain inflated and will likely stay in the $1.5/Gb-$2.0/Gb range. HBM pricing will likely reach $5/Gb-$6/Gb by 2030. Based on this, the general DRAM market size will be around $1.10T-$1.46T and the HBM market will be around $1.50T-$1.80T. The total DRAM market will be around $2.60T-$3.26T (midpoint $2.93T). If ASP rises further, then the market size will further increase.

You can contact me through citrini.com for more info.