The market and a number of recent reports have grown bearish on memory. The thesis runs that the wave of capacity additions arriving around 2027 and 2028 will let supply catch up with demand, prices will roll over, and a de-rating will follow just as the old cyclical script dictates.
I disagree with that view.
The bear case still prices memory as a commodity, and the technological terrain underneath that assumption is changing right now. Trace the structural shift underway in the memory industry at the engineering level and it becomes clear that the “same standard part no matter who makes it” premise, the one the cycle-top argument leans on, applies less and less to the memory that is coming.
At the center of that shift is the HBM base die.
The base die moves to a logic process, customer circuitry moves into it (cHBM), and at the end the memory sits directly on top of the customer’s compute die (memory-on-logic).
I expect that at the end of this progression memory companies will shift from commodity manufacturers toward custom silicon partners, and the way memory companies are moving today points in that direction. This article walks through the technical background, the actual moves being made across the industry, and what this change means for memory revenue structure and valuation. By the end, you will understand why I remain bullish on memory, and why that reasoning rests on a change in the structure of the memory business itself.
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Table of Contents
- HBM, cHBM, and memory-on-logic, three structures distinguished
- From cHBM to memory-on-logic, the order in which the industry is moving
- What Silicon Valley is hearing
- How the memory revenue structure changes
- What to watch from an investment standpoint
Disclaimer
The figures and timelines in this article are drawn from company announcements, public reporting, and published papers. The interpretation of those figures and the outlook expressed here are entirely my own analysis, and nothing here constitutes a recommendation to buy or sell any specific security. Responsibility for investment decisions and their outcomes rests with the individual investor.
1. HBM, cHBM, and memory-on-logic, three structures distinguished
HBM
HBM (High Bandwidth Memory) stacks DRAM dies eight, twelve, or sixteen high and connects them vertically with TSVs (Through-Silicon Vias). At the bottom of the stack sits the base die. It handles memory control, I/O, and test logic, and serves as the gateway that links the DRAM stack to the outside world. The finished HBM stack is placed beside the GPU on a silicon interposer and connects to the GPU through the interposer’s wiring. The stack itself is 3D, but because it sits side by side with the GPU rather than on top of it, the arrangement is called 2.5D. In HBM4 the interface between the GPU and the stack is 2,048 bits wide, and those signals leave the PHY at the edge of the GPU die, cross the interposer wiring, and pass into the base die.
The DRAM core dies above are largely fixed in structure, since the capacitor array that stores data occupies most of their area, so the only layer in the stack that carries logic is the base die at the bottom. Every byte moving between the GPU and memory passes through this layer, which makes the base die’s processing capability the determinant of the entire stack’s bandwidth and power efficiency, and that burden grows with each generation. The interface has doubled from 1,024 bits in HBM3 to 2,048 bits in HBM4, per-pin speed has risen alongside it, and the complexity of signal processing, channel management, and power management has climbed with each step.
For that reason memory companies have worked on the base die first when improving HBM performance, and the starting point was the process used to build it. Through HBM3E the base die was fabricated on a DRAM process, the same as the DRAM dies above it. A DRAM process is specialized for high capacitor density, so putting logic circuitry on it yields something larger and slower than the same logic built on a logic process. The work the base die must do grows every generation, and a DRAM process cannot keep pace, so from HBM4 the base die began moving to a logic process.
SK hynix builds it on TSMC’s 12nm process and Samsung on its own foundry’s 4nm process, while Micron alone keeps the base die on its existing DRAM process through HBM4 on cost grounds and plans to move to a TSMC logic process from HBM4E.
Even with the process change, though, the design of this base die still belongs to the memory company, and the product remains a standard part conforming to JEDEC specifications.
cHBM
Moving the base die to a logic process does not remove the problem built into the HBM structure. The GPU side is chronically short of die area for computation, and part of that scarce area is taken up by data-moving circuits such as the HBM interface and the memory controller.
This is where the concept of cHBM (custom HBM) begins.
The idea is to push the circuits on the GPU side that communicate with memory down into the base die, which sits directly beneath the memory stack anyway. The GPU then spends the freed area on computation, and the memory-related logic runs right below where the data is stored. Handle preprocessing or compression in that same spot and the volume of data that has to travel to the GPU falls, which saves power as well.
The catch is that a JEDEC-standard base die is the common denominator for every customer, so it has no room for this kind of relocation tuned to a specific customer’s architecture. In other words, cHBM is the approach of departing from the standard and designing the base die in a custom way to build the HBM. As an aside, the industry sometimes refers to conventional HBM that follows the standard as sHBM (standard HBM).
There are several ways to design a cHBM base die. They range from the memory company designing it to the customer’s specification, to an ASIC (Application-Specific Integrated Circuit) partner such as Marvell defining the base die jointly with the three memory makers, to the customer designing the base die logic directly, as NVIDIA does.
In every form the memory stack and the logic have to operate as one, and the customer’s design specifications or circuits enter the base die, so the two sides have no choice but to sit together and define the specification from the earliest stage of design.
What does it mean for part of a customer’s circuitry to be designed into the base die.
It means the business model of memory, long regarded as a commodity, begins to shift from this point. An HBM carrying a customer’s circuitry is that customer’s dedicated part and cannot be sold elsewhere, and from the customer’s side, memory with its own circuitry embedded cannot easily be swapped for another supplier’s product. The commodity premise that anyone’s part is interchangeable as long as the spec matches no longer holds from cHBM onward.
memory-on-logic
By the time you reach cHBM, the base die looks less like a chip for managing memory and more like the customer’s logic chip. The interface belongs to the customer, so does the controller, and so do the functions filling the remaining area. That raises a new question. Is there a reason to build a separate base die at all. Why not place the GPU proper, the compute die, in the base die’s position and stack the memory directly on top of it. That structure is memory-on-logic. The compute die absorbs everything the base die used to do, the interposer disappears, and the memory stack is stacked in 3D directly on top of the compute die.
At this point the physical conditions of the connection change. Instead of joining the HBM stack and the GPU through a 2,048-bit edge interface, the connection points spread across the entire bonded interface. Vertical bonding methods such as TSV and hybrid bonding push the connection density from tens of thousands to hundreds of thousands, and the distance a signal travels shrinks from the millimeters of interposer wiring to tens of micrometers in the vertical direction.
Bandwidth changes by an order of magnitude, and so does the energy needed to move a bit. A 2025 paper from Georgia Tech and SK hynix analyzed a memory-on-logic structure as capable of 64 times the throughput and three times the energy efficiency of 2.5D. The numbers are academic modeling and need not be taken at face value, but they are a good illustration of the direction and magnitude of the improvement.
The unsolved problem with memory-on-logic is heat. Place DRAM on top of a compute die burning hundreds of watts and the DRAM blocks the compute die’s thermal escape path while absorbing that heat itself. And DRAM, which is sensitive to temperature, sees its refresh interval shorten under heat, opening the door to degraded performance. In the end, how this heat problem is solved is likely to be the single largest variable determining the success of memory-on-logic.
The story so far starts not with HBM as a whole but with a single die at the bottom of the stack.
That base die moves from a DRAM process to a logic process (HBM4), customer logic moves into it (cHBM), and finally the base die’s position is taken by the customer’s compute die (memory-on-logic).
This progression need not be read as a linear generational replacement, however. cHBM is the most realistic commercialization path for the next several years, while memory-on-logic is a more radical structure that reaches the mainstream only once the heat and yield problems are solved. Rather than one immediately replacing the other, the two structures are likely to be adopted in parallel for some time, depending on the customer’s power budget, workload, and packaging cost.
The closer the base die moves to the customer’s silicon, the closer the memory business moves to a custom silicon business, and….
I think this is precisely the point the market has yet to properly grasp about the upside in the memory business.
The three memory makers are still valued as cyclical stocks that move on bit growth and ASP, and the changes in revenue and margin structure that the custom transition will produce have never yet shown up in reported numbers, so they have had no opportunity to be reflected in valuation models. That is how significant this change is, and exactly how the business model and revenue structure change is covered in detail below.
2. From cHBM to memory-on-logic, the order in which the industry is moving
cHBM is already visible on product roadmaps. Application of cHBM keeps coming up for the NVIDIA Feynman generation slated for 2028, though NVIDIA has not officially confirmed the details, so this is better treated as a key point to watch for that generation than as an established fact. Samsung, SK hynix, and Micron have all placed custom HBM on their official roadmaps, and Marvell has announced that it is co-developing a custom HBM architecture with the three memory makers. The shift of customer-specific base dies into the place of standard base dies has already entered the execution stage.
While cHBM settles onto roadmaps, the next stage, memory-on-logic, has produced its own case with a disclosed production timeline.
That is Qualcomm’s HBC (High Bandwidth Compute), unveiled at its June 2026 Investor Day.
It is not yet a product on the market. The AI250 accelerator carrying HBC Gen1 is slated to launch in mid-2027, with Gen2 on the follow-on roadmap. HBC belongs to the memory-on-logic family, but the memory is LPDDR (Low Power DDR) rather than HBM, and the die placed beneath the stack is a dedicated near-memory accelerator rather than the GPU proper.
Consider the structure. Qualcomm separated the AI accelerator from the SoC. It stacks an LPDDR stack on top of the separated accelerator die and connects them with TSVs. This HBC unit and the SoC sit side by side on an ordinary organic substrate. There is no silicon interposer, and no 2.5D advanced packaging such as CoWoS. The design is meant to route around two bottlenecks at once, the HBM supply shortage and the shortage of advanced packaging capacity.
Qualcomm chose LPDDR for capacity and power. LPDDR is a DRAM family designed for low power, so the power burden per stack is small and it lends itself to capacity expansion. Qualcomm’s answer to the memory-on-logic heat problem sits right here. Rather than the hot GPU proper, it places a low-power dedicated accelerator underneath, and uses low-power LPDDR for the memory as well, so the whole thing fits within the thermal budget.
Qualcomm claims six times the bandwidth per watt of HBM and 200 times the capacity per watt of on-chip SRAM. The stated figures will need a detailed whitepaper and real hardware to verify, but movement on the customer side has already appeared.
Saudi Arabia’s Humain has included AI250 racks carrying HBC Gen1 in its deployment plans, and according to reports Microsoft’s Nadella also spoke of deploying Qualcomm HBC in Azure data centers. That a product still a year from launch already has the names of a large infrastructure customer and a hyperscaler circulating around it is itself evidence of demand for this structure.
Qualcomm is not the only one moving toward memory-on-logic.
There were reports that SK hynix had been discussing, since 2023, a method of stacking HBM directly on top of a processor with several fabless companies including NVIDIA, and a manufacturing approach of bonding memory onto a logic wafer using TSMC’s wafer bonding came up alongside it.
Taiwan’s ASIC design house GUC has proposed DoL (DRAM-on-Logic), placing one to four layers of DRAM on top of logic. Whether what goes on top is LPDDR or an HBM-style DRAM stack, and whether the logic underneath is a dedicated accelerator or the GPU proper, varies from case to case, but the direction is the same in every one, memory drawing steadily closer to logic until it finally sits on top of it.
And as noted, memory sitting on top of logic means memory becoming one body with a specific customer’s chip.
At the end of this progression from cHBM to memory-on-logic, the memory business gradually turns into a custom silicon business, and what Silicon Valley has been hearing lately suggests that the change has already begun at the organizational level.
So what matters from an investment standpoint.
It is how this shift toward memory companies becoming custom silicon companies changes their revenue structure, where along the supply chain the profit moves, and what to track the progression by. These are the things to focus on. What follows below covers them in detail.
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3. What Silicon Valley is hearing
There is one more piece of evidence that memory-on-logic is a real trend.
The full article is available on Substack.
Please refer to the link below.
